In general, DRAM (Dynamic Random Access Memory) and other volatile memories are currently designed to JEDEC (JEDEC Solid State Technology Association) specifications covering LPDDR2 (Low Power Double Data Rate 2). In LPDDR2, the DPD (Deep Power Down) state is specified. In the DPD state the DRAM element is cutoff from the outside electric source to reduce electric power consumption during the waiting state.
However, when the DRAM element transitions to the DPD state the data stored in the memory vanishes. Therefore, when the element returns to the idle state (the electric passage state) from the DPD state, it is necessary to rewrite (initialize) the data to the memory again. Therefore, it takes a relatively long time and a large electric power consumption to return from the DPD state. Thus, in a system using DRAM, or other volatile memories, the memory element is often maintained in an idle state, which has a shorter return time than the DPD state, instead of the DPD state.
In the idle state, it is necessary to carry out a refreshing action periodically to maintain the data inside the memory. Therefore, even in the idle state, electric power is still required to a certain extent.
During the transition from the idle state to the DPD state considerable electric power is consumed when the electric power is supplied to the cutoff portion of the memory element. Therefore, if the DPD state is entered for just a short interval before the return to the idle state, significant electric power is consumed during the return and potentially no overall power savings will be realized from entering the DPD state.